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[VHDL-FPGA-Verilog] VLSIrtl_spi

Description: verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
Platform: | Size: 46080 | Author: citybus | Hits:

[Other] verilog_lcd

Description: 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Platform: | Size: 423936 | Author: yhr | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[CSharp] SPIinterfaceEEPROMcontrol

Description: SPI接口EEPROM的控制，根据SPI的时序特征，编写AT93c46的读写程序-SPI EEPROM control, according to the chronology of SPI, AT93c46 literacy preparation procedures
Platform: | Size: 1024 | Author: zhanya | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473088 | Author: Jack | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[VHDL-FPGA-Verilog] vspi

Description: SPI的verilog实现，非常的全面和详细，还带有spi算法的注解！-SPI s Verilog realization, very comprehensive and detailed, but also with the annotation algorithm spi!
Platform: | Size: 7168 | Author: 王和国 | Hits:

[VHDL-FPGA-Verilog] MXIC-SPIFlash-Model

Description: Verilog based simluation model for MXIC SPI Flash.-err
Platform: | Size: 77824 | Author: ronsullivan | Hits:

[VHDL-FPGA-Verilog] I2C_HDL

Description: I2C bus HDL source and testbench
Platform: | Size: 701440 | Author: liuKe | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[Com Port] pwm16bits

Description: SPI总线Master的verilog代码-SPI Bus Master of Verilog code
Platform: | Size: 1024 | Author: xudong | Hits:

[VHDL-FPGA-Verilog] SPI

Description: Verilog SPI 源码（来自网络）-Verilog SPI
Platform: | Size: 49152 | Author: lanbow | Hits:

[VHDL-FPGA-Verilog] spiflash_ctrl

Description: VHDL 语言实现的SPI FLASH的读写-VHDL language to read and write of the SPI FLASH
Platform: | Size: 6144 | Author: 李天鸿 | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] ad_test

Description: ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现-ad9777 test procedures, the SPI is initialized, the use of ISE environment, the successful realization of comprehensive and
Platform: | Size: 2665472 | Author: 关明明 | Hits:

[VHDL-FPGA-Verilog] spi_verilog

Description: SPI协议Verilog HDL程序，内含testbench 文件
Platform: | Size: 81920 | Author: dsahd | Hits:

[VHDL-FPGA-Verilog] spi

Description: this the SPI slave module -this is the SPI slave module
Platform: | Size: 2782208 | Author: David | Hits:

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